JPS6370548A - 半導体装置用リ−ドフレ−ム - Google Patents

半導体装置用リ−ドフレ−ム

Info

Publication number
JPS6370548A
JPS6370548A JP61216342A JP21634286A JPS6370548A JP S6370548 A JPS6370548 A JP S6370548A JP 61216342 A JP61216342 A JP 61216342A JP 21634286 A JP21634286 A JP 21634286A JP S6370548 A JPS6370548 A JP S6370548A
Authority
JP
Japan
Prior art keywords
tie bar
cut
resin
tie
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61216342A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0545063B2 (en]
Inventor
Toshiaki Shinohara
利彰 篠原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP61216342A priority Critical patent/JPS6370548A/ja
Publication of JPS6370548A publication Critical patent/JPS6370548A/ja
Publication of JPH0545063B2 publication Critical patent/JPH0545063B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
JP61216342A 1986-09-12 1986-09-12 半導体装置用リ−ドフレ−ム Granted JPS6370548A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61216342A JPS6370548A (ja) 1986-09-12 1986-09-12 半導体装置用リ−ドフレ−ム

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61216342A JPS6370548A (ja) 1986-09-12 1986-09-12 半導体装置用リ−ドフレ−ム

Publications (2)

Publication Number Publication Date
JPS6370548A true JPS6370548A (ja) 1988-03-30
JPH0545063B2 JPH0545063B2 (en]) 1993-07-08

Family

ID=16687046

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61216342A Granted JPS6370548A (ja) 1986-09-12 1986-09-12 半導体装置用リ−ドフレ−ム

Country Status (1)

Country Link
JP (1) JPS6370548A (en])

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0298165A (ja) * 1988-10-05 1990-04-10 Goto Seisakusho:Kk 電子部品用リードフレーム及びこれを用いた電子部品の製造方法
JPH03257836A (ja) * 1990-03-07 1991-11-18 Rohm Co Ltd 合成樹脂封止型電子部品におけるモールド部の成形方法
JPH04121755U (ja) * 1991-04-22 1992-10-30 ローム株式会社 電子部品用リードフレームの構造
US5821610A (en) * 1995-01-18 1998-10-13 Nec Corporation Leadframe allowing easy removal of tie bars in a resin-sealed semiconductor device
US6444905B1 (en) * 1998-12-24 2002-09-03 Hitachi, Ltd. Semiconductor device
US20130341779A1 (en) * 2012-06-25 2013-12-26 Mitsubishi Electric Corporation Method of manufacturing a semiconductor device and semiconductor device
CN116690399A (zh) * 2023-08-07 2023-09-05 烟台一诺电子材料有限公司 一种键合丝抛光涂层一体化装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS525584U (en]) * 1975-06-27 1977-01-14
JPS533011U (en]) * 1976-06-25 1978-01-12
JPS5988854A (ja) * 1982-11-12 1984-05-22 Toshiba Corp 半導体装置
JPS59134857A (ja) * 1983-01-21 1984-08-02 Toshiba Corp 半導体装置
JPS6123348A (ja) * 1984-07-12 1986-01-31 Nec Corp 樹脂封止型半導体装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS525584U (en]) * 1975-06-27 1977-01-14
JPS533011U (en]) * 1976-06-25 1978-01-12
JPS5988854A (ja) * 1982-11-12 1984-05-22 Toshiba Corp 半導体装置
JPS59134857A (ja) * 1983-01-21 1984-08-02 Toshiba Corp 半導体装置
JPS6123348A (ja) * 1984-07-12 1986-01-31 Nec Corp 樹脂封止型半導体装置

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0298165A (ja) * 1988-10-05 1990-04-10 Goto Seisakusho:Kk 電子部品用リードフレーム及びこれを用いた電子部品の製造方法
JPH03257836A (ja) * 1990-03-07 1991-11-18 Rohm Co Ltd 合成樹脂封止型電子部品におけるモールド部の成形方法
JPH04121755U (ja) * 1991-04-22 1992-10-30 ローム株式会社 電子部品用リードフレームの構造
US5821610A (en) * 1995-01-18 1998-10-13 Nec Corporation Leadframe allowing easy removal of tie bars in a resin-sealed semiconductor device
US6444905B1 (en) * 1998-12-24 2002-09-03 Hitachi, Ltd. Semiconductor device
US6541702B2 (en) 1998-12-24 2003-04-01 Hitachi, Ltd. Semiconductor device
US6553657B2 (en) 1998-12-24 2003-04-29 Hitachi, Ltd. Semiconductor device
US6777262B2 (en) 1998-12-24 2004-08-17 Renesas Technology Corp. Method of packaging a semiconductor device having gull-wing leads with thinner end portions
US20130341779A1 (en) * 2012-06-25 2013-12-26 Mitsubishi Electric Corporation Method of manufacturing a semiconductor device and semiconductor device
US8859338B2 (en) * 2012-06-25 2014-10-14 Mitsubishi Electric Corporation Method of manufacturing a semiconductor device and semiconductor device
DE102013200944B4 (de) * 2012-06-25 2020-10-15 Mitsubishi Electric Corp. Verfahren zum Herstellen einer Halbleitervorrichtung und Halbleitervorrichtung
CN116690399A (zh) * 2023-08-07 2023-09-05 烟台一诺电子材料有限公司 一种键合丝抛光涂层一体化装置
CN116690399B (zh) * 2023-08-07 2023-09-26 烟台一诺电子材料有限公司 一种键合丝抛光涂层一体化装置

Also Published As

Publication number Publication date
JPH0545063B2 (en]) 1993-07-08

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